The present invention relates generally to semiconductor device manufacturing and, more particularly, to creating anisotropically diffused junctions in field effect transistor (FET) devices.
As the pitch between individual devices on integrated circuits (ICs) continues to shrink with each new technology generation, elements of these devices such as transistor gate electrodes, spacers and source and drain diffusion extents, both lateral and vertical, are required to be sized down accordingly. As a result, FET scaling has become a significant challenge in the semiconductor industry. Traditional scaling techniques such as shallower implants and reduced thermal budgets begin to fail as device dimensions shrink down to the nanometer (nm) regime because control of the abruptness and shallowness of the doping profiles is limited due unavoidable transient-enhanced diffusion. One well-known method to mitigate the inability to create increasingly abrupt and shallow junctions is anti-punchthrough (APT) or halo implantation. These halo implants shield the increasingly small FET channel regions from the encroachment of the source and drain implants and thus help to reduce deleterious short channel effects (SCE). However the resulting highly doped channels or pocket implant regions degrade device performance and power consumption by increasing junction capacitance and band-to-band tunneling.
Moreover, traditional scaling requires the simultaneous reduction of both lateral and vertical dimensions of the transistor, including gate pitch, gate thickness, and source/drain (S/D) junction depth, in order to maintain reasonable short channel control from one node to the next. However, in the sub 90 nm technology nodes, where S/D stress-inducing elements such as eptiaxially grown silicon germanium (eSiGe) and silicon carbon (eSiC) are incorporated for carrier mobility enhancement, scaling the S/D junction depth results in device performance degradation due to stress loss. Additionally, the shallower junctions result in higher S/D series resistance, further degrading the scaled device performance. Finally, in high-performance silicon-on-insulator (SOI) technologies, some portion of the source and drain junctions of each device must encroach sufficiently on the buried insulator, a condition referred to as “butting”, in order to isolate adjacent devices that occupy the same contiguous silicon region. Since a typical FET (NFET) junction is formed via self-aligned dopant implantation and subsequent thermal annealing, or by a self-aligned cavity etch and subsequent fill by a heavily in-situ doped strained silicon alloy, a relatively large spacer and high halo implant is typically utilized in order to prevent short channel degradation from the lateral encroachment of the deep source/drain.